TALOS™


Talos ES™ is a modern mini-computer built with 74-series logic and featuring a custom, 3-stage pipelined RISC CPU capable of up to five different, parallel operations every clock cycle. It is meant for education (targeted at both hobbyists and undergraduate students of computer engineering) and entertainment. A diagrammatic overview of the microarchitecture of Talos ES™'s custom RISC CPU can be found here.



Although designed to be an educational toy, Talos ES™ is meant to be a truly usable toy, in the sense of being reliable, convenient to operate and capable of running significant applications. It opts for a RISC CPU because old-fashioned CISC microarchitectures are no longer relevant today. Nonetheless, it aims at being easily programmable at assembly level, despite its pipelined structure. Only currently-manufactured, standard parts are used to facilitate procurement. LED bars are used throughout to provide real-time monitoring of the computer's data, address and control lines.



Each card in Talos ES™ is also built to be used in two different modes: as a standalone device, whose lines can be driven from integrated DIP switches, or as part of the whole system running at maximum speed. This enhances both the educational and entertainment possibilities of the mini-computer.


The "ES" in "Talos ES™" stands for 'Eight-Sixteen': Talos has an external 8-bit data bus and, as such, is an 8-bit computer. However, its CPU has an internal 16-bit bus and is able to perform both ALU and register-to-register operations on 16-bit operands. This allows Talos ES™ to perform 16-bit address calculations directly (without tricks such as the 6502's zero page scheme), or multiple 8-bit operations in parallel.




The development of the Talos ES™ project has been chronicled in an series of YouTube videos. It comprises a motherboard and four distinct cards (connected to the motherboard via backplane connectors) making up the RISC CPU. All design, simulation and manufacturing files are available on Talos ES™'s Github directory, as the design progresses.

A cost-reduced version, called Talos CR™, will be developed (early) in 2024. It will consist of a single board with mostly SMD components. This version will be sent to developers to seed a firmware and software ecosystem.

Technical specifications

  • Shallow pipeline
  • Stage 1: Instruction fetch (1 clock cycle) 
  • Stage 2: Instruction decode (1 clock cycle) 
  • Stage 3: Instruction execution (1 clock cycle)

  • Orthogonal operations
  • Memory access operations 
  • Register-to-register operations 
  • Logic and arithmetic operations

  • 8/16-bit ALU operations
  • Two 8-bit ALU operations per cycle, or… 
  • One 16-bit ALU operation per cycle

  • Instruction-Level Parallelism (ILP)
  • Up to 5 different (MIMD), parallel 8-bit operations per cycle