The development of Talos ES™, chronicled over a year-long series of fairly technical videos, is now complete. You can watch the last video here:
In the video, I demonstrate the firmware (including the minimalistic assembler) and show a couple of mathematical applications running on the system. The Instruction Level Parallelism (ILP) of the microarchitecture is exploited for maximum performance. Indeed, Talos ES™ has exceeded its design goal of up to four parallel operations per cycle, and is now running up to five operations concurrently. The video is a 1.5-hour special that is really worth watching, I think!
The next step in the Talos universe will be the development of Talos CR™, a Cost-Reduced version of the system based on a single board and mostly SMD components. This version will be sent to developers so to seed a firmware and software ecosystem. After Talos CR™, I plan to develop an FPGA-based soft core of the Talos CPU, intended to demonstrate its possible feasibility as a very-low-cost Digital Signal Processor (DSP) in custom silicon.
To learn more about Talos ES™, check out the project's homepage. All project files are also available, under the extremely permissive MIT license, on Github.