This is as unfortunate a shortcoming of engineering education as it is unjustified: putting a working computer together from scratch isn’t difficult, and it can give students critical early confidence in their ability to live up to the label ‘computer engineer.’ Moreover, the lack of system-level understanding is a noticeable performance limiter among unexperienced staff in the industry; so much so that some larger companies—such as Philips Semiconductors, today’s NXP—used to offer internal ‘system architecture’ education to close the gap.
CERBERUS 2100™ is an educational system meant to help address this issue. While being a complete and fully functional computer, it illustrates—down to the level of individual gates and flip-flops—how a relatively complex, multi-processor system can be built. Moreover, it allows for experimentation at both firmware and hardware levels, as the system is built around three in-system programmable CPLDs and an AVR I/O controller. CERBERUS features both Z80 and W65C02S CPUs, exposing students to different instruction sets so they can be contrasted. And it can even be augmented with extra cards and CPUs through an expansion protocol that allows Direct Memory Access (DMA).
As such, CERBERUS 2100™ is a sandbox for computer engineering experimentation and learning. Students can change the firmware—which is an Arduino sketch written in C—to suit their purposes, reprogram the hardware in the three CPLDs through a simple JTAG interface, design their own expansion cards, and write assembly (or BASIC) code for the CPUs.
A key design challenge to render this level of flexibility possible was to partition the architecture into three largely self-contained, asynchronous, modular domains. These allow students to modify and experiment with any one domain in isolation, without breaking the other two. And since they start from a working system, students can get immediate feedback on the performance of their changes and iterate quickly. The barrier-to-entry for trying out ideas is minimal.
The three modular domains in CERBERUS 2100™ are: the video circuit, the computer proper, and the expansion circuit. To allow the video circuit to operate asynchronously and independently of the computer proper, two Dual-Ported (DP) SRAM ICs are used as video and character memories. The computer proper can write to these memories using one of their ports, while the video circuit asynchronously reads from them using the other. The expansion circuit and the computer proper also operate asynchronously, thanks to a memory-mapped communication protocol implemented in the firmware, which runs on the AVR I/O controller.
FAT-CAT™ is just an affectionate name for the ATmega328PB I/O controller: it manages the µSD card, keyboard, buzzer, and expansion protocol. Because the firmware resides in the internal flash of FAT-CAT™, it occupies no address space, leaving the entire 64KB available to user code.
The next figure provides an overview of the board, highlighting the key ICs and the three asynchronous, modular domains.
A key challenge for the design of FAT-SPACER™ was the fact that CERBERUS 2100™ is an expandable multi-processor system: the three processors and expansion logic have very different control signals, so a standard control bus was out of question. Instead, FAT-SPACER™ comprises a fully connected control nexus, which manages all control inputs and outputs of the processors and memories according to internal Boolean logic.
The choice of CPLDs for the chipset was meant to advance the educational goal: unlike FPGAs and their high-level synthesis tools, CPLD design entries contain a gate-level description of the hardware—essentially, they are schematics in written form. This allows students to see exactly what is going on. Moreover, with CPLDs any change to the Boolean logic implemented does not change the propagation delay through the IC. This means that students can change FAT-SPACER™, FAT-CAVIA™, and FAT-SCUNK™ without worrying about timing issues—only the logic matters. This is an important feature for making the platform accessible.
The choice of an AVR microcontroller to host the firmware was also meant to advance CERBERUS’s educational goal: modifying a C sketch from within the Arduino IDE is a much more attractive proposition to students than re-writing assembly-level kernel code.
CERBERUS 2100™ deliberately lacks advanced graphics capabilities so to avoid ‘black box’ Systems-on-a-Chip and Systems-in-a-Package, such as the ESP32 used in my own Agon light™ platform. The opacity of these highly integrated ICs would have defeated CERBERUS’s educational goal, whereby the point was precisely to avoid black boxes. Instead, CERBERUS makes everything—except for the three processors—visible and accessible down to the level of individual gates and flip-flops. In the video circuit, this admittedly limits the number of registers available. The advantage, however, is that students can see all the details of how the VGA signal is generated from information in video and character memories, including all the associated counters, product terms, shift-register, reset circuitry, etc.
CERBERUS 2100™ runs BASIC interpreters on both of its CPUs. The interpreters were ported by Alexander Sharikhin (W65C02S) and Dean Belfield (Z80), who also significantly improved my original firmware. CERBERUS is the result of our collaboration. We hope it will be as useful to faculty—and enjoyable to students—as it has been fun for us to build.
You can find more about the system in its homepage and Github repository. For the latest news and developments, join the developers' group. And there is also a video demonstration of the system available on YouTube: